Design-Reuse

Improving ASIC Design Verification using FPGAs and Structured ASICs

Structured ASICs require developers to re-program only the top level metal layers when customizing their designs, enabling faster development time and low unit cost. However, many structured ASICs ...
Semiconductor Engineering

Beyond The Water Cooler: 2020 Report On IC/ASIC Design And Verification Trends

Verification and design engineers like to talk shop and discuss their experiences and visions. But even though engineers sharing stories around the water cooler (whatever form that takes—conferences, ...
Semiconductor Engineering

ASIC/IC Verification Trends With A Focus On Factors Of Silicon Success

At long last we come to the final installment of our four-part series presenting the findings of the Wilson Research Group Functional Verification 2020 study. In this article we discuss verification ...
Outlookindia

Bridging The Talent Gap In ASIC Design, Verification, And Silicon Validation

As technology continues to evolve, the need for semiconductor chips also increases. The semiconductor industry lies underneath much of the technological progress, powering devices and systems that ...
EDN

Pre-configured DFT structures can simplify ASIC design, verification

Steven Kawamoto, Sr. Marketing Manager, Custom LSI Solutions Unit, Gaku Ogura, Sr. Marketing Manager, Design Solutions Center, Richard Lee, Design Engineer, Design ...
Business Wire

Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM™ simulation ...