San Jose, Calif. – Tool startup Silicon Dimensions Inc. has released an add-on to its Chip2Nite floor planner, block design and analysis offering that will let logic designers repair physical defects ...

As technology nodes shrink down, the supply voltages of CMOS circuits are scaled down too, and because of that, standby leakage current increases, becoming significant. Until recent years, area and ...

There’s an old saying that the first 90% of a task takes 90% of the schedule, and the remaining 10% takes the other 90% of the time. In chip development, design-signoff closure has become one such ...

In recent years, we have seen a clear market trend towards dedicated integrated circuits (ASICs) that are much more efficient in performance and energy consumption than traditional general-purpose ...

At its introduction almost three years ago, Zenasis Technologies' ZenTime was marketed as a standard cell-optimization tool largely for integrated device manufacturers (IDMs). But Zenasis has ...